1. Field of the Invention
This invention relates generally to a semiconductor fabrication process, and, more particularly, to detecting faults across multiple semiconductor processes.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in continual improvements in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
During the fabrication process, various events may take place that affect the performance of the devices being fabricated. That is, variations in the fabrication process steps may result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the device. Various tools in the processing line are controlled, in accordance with performance models, to reduce processing variation. Commonly controlled tools include photolithography steppers, polishing tools, etching tools, and deposition tools. Pre-processing and/or post-processing metrology data is supplied to process controllers for the tools. Operating recipe parameters, such as processing time, are calculated by the process controllers based on the performance model and the metrology information to attempt to achieve post-processing results as close to a target value as possible. Reducing variation in this manner leads to increased throughput, reduced cost, higher device performance, etc., all of which equate to increased profitability.
Semiconductor manufacturing processes, which have become more reliable and robust over the past few years, may include a plurality of processing tools that cooperate with each other to process semiconductor devices, such as microprocessors, memory devices, ASICs, etc. To verify that the processing tools are operating within acceptable parameters, it has become increasingly desirable to monitor the operating conditions of such processing tools.
Today's semiconductor manufacturing processes may include an intricate network of multiple processing tools for manufacturing semiconductor devices. Linking multiple processing tools may provide numerous advantages in the manufacture of semiconductor devices, but there can, however, be some drawbacks, particularly from the standpoint of troubleshooting problems or faults. For example, assume that two processing tools are “linked” due to their interdependency on each other to provide a desired result. If results or performance from the upstream processing tool are not predictable or on target, the wafer resulting from a downstream process can be unacceptable even though the downstream tool performed as expected. A fab technician may expend considerable time analyzing the downstream processing tool even though the actual cause of the fault lies with the upstream tool. Not surprisingly, when more than two separate processes are “linked,” trouble shooting problems can become even more challenging. Failure to identify, in a timely manner, the source of the detected faults may naturally delay any potentially corrective measures that can be taken to address the problem. Because of these delays, the operation of the semiconductor manufacturing process may be adversely affected, thereby resulting in a potential increase in costs for the manufacturer and consumer.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.